Digital phase-locked loops (PLL) require a form of time-to-digital conversion, which produces digitized phase error information. Analog PLLs require a phase and frequency detector (PFD). However, the time-to-digital convertor (TDC) is a circuit which requires accurate delay definition and resolution and such a circuit when implemented in an integrated circuit suffers from process variation and power supply noise which degrades the accuracy of the time to digital conversion. In addition, the TDC is a non-linear circuit and produces quantization noise due to its finite discrete delay resolution unlike the continuous phase resolution of PFDs. The TDC in a digital PLL produces non-linearities which degrade the system performance by producing frequency spurs in the output signal. The TDC therefore causes limitations on the PLL phase noise performance from finite limit cycles and excessive quantization noise.
One way to achieve higher linearity is by increasing the resolution of the TDC. A high resolution multi-bit TDC is widely used as it explicitly improves the linearity while reducing its quantization noise. However, a multi-bit TDC also increases circuit complexity and it often relies on accurate and precise circuit propagation delay units (i.e., least significant bits (LSB) of resolution) which in a practical circuit implementation is susceptible to process variations and power supply noise (e.g., 5 bit TDC has 32 delay stages). Another approach is to dither the reference clock in time. This dithering results in a higher input noise contribution from the reference clock resulting in high phase noise. Another approach is simply to ignore the non-linear effect, and assume the non-linear TDC as a linear TDC with quantization noise injected. However, this often prevents accurate system dynamic analysis and increases the sensitivity to other system non-linearities such as loop delay.